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ESP32-P4-Module User Guide

Overview

Introduction

ESP32-P4-Module is a dual-core RISC-V high-performance module based on ESP32-P4 chip designed by Waveshare, using ESP32-C6H8 to expand WIFI6 functionality. It supports a wide range of human-computer interfaces, including MIPI-CSI (Integrated Image Signal Processor, ISP) and MIPI-DSI interfaces, as well as common peripherals such as SPI, I2S, I2C, LED PWM, MCPWM, RMT, ADC, UART, and TWAI™. It also supports USB OTG 2.0 HS, Ethernet, and SDIO Host 3.0 for high-speed connectivity. The chip integrates a digital signature peripheral and a dedicated key management unit to ensure its security. ESP32-P4-Module is specifically designed for high-performance and high-security applications, fully meeting the higher demands of embedded applications for human-machine interface support, edge computing capabilities, and IO connectivity features.

Features

  • Processor
    • Equipped with RISC-V 32-bit dual-core processor (HP system), it features DSP and instruction set expansion, along with floating point unit (FPU), and the main frequency is up to 400MHz
    • Equipped with a RISC-V 32-bit single-core processor (LP system), the main frequency is up to 40MHz
    • Equipped with ESP32-C6 WIFI/BT co-processor, expand WIFI 6/Bluetooth 5 and other functions through SDIO
  • Memory
    • 128 KB of high-performance (HP) system read-only memory (ROM)
    • 16 KB of low-power (LP) system read-only memory (ROM)
    • 768 KB of high-performance (HP) L2 memory (L2MEM)
    • 32 KB of low-power (LP) SRAM
    • 8 KB of system tightly coupled memory (TCM)
    • 32 MB PSRAM is stacked in the package, and the QSPI port is connected to 16MB Nor Flash

Pinout Definition


Dimensions


Pinout Description

1GNDGround pin
2LNA_OUTAntenna pin of ESP32-C6, led to the pin pad by default and can be switched to an IPEX Gen 1 antenna holder via a reserved 0R resistor
3GNDGround pin
4C6_U0RXDUART RXD of ESP32-C6, for flashing firmware to ESP32-C6
5C6_U0TXDUART TXD of ESP32-C6, for flashing firmware to ESP32-C6
6C6_IO15ESP32-C6 GPIO15
7C6_IO14ESP32-C6 GPIO14
8C6_IO13ESP32-C6 GPIO13
9C6_IO9ESP32-C6 GPIO9; If C6_SPIO8 is in pull-up mode, it can enter download mode when pulled down before power-onC6_BOOT
10C6_IO8ESP32-C6 GPIO8; It is recommended to pull up 10k resistor to 3.3VC6_BOOT_EN
11C6_IO7ESP32-C6 GPIO7; C6 JTAG GPIOMTDO
12C6_IO6ESP32-C6 GPIO6; C6 JTAG GPIOMTCK
13C6_IO5ESP32-C6 GPIO5; C6 JTAG GPIOMTDI
14C6_IO4ESP32-C6 GPIO4; C6 JTAG GPIOMTMS
15GNDGround pin
16GPIO1GPIO1, can be connected with GPIO0 to 32.768KHz crystal oscillator, LP system crystal sourceXTAL_32K_P
17GPIO2GPIO2TOUCH_CHANNEL0
18GPIO3GPIO3TOUCH_CHANNEL1
19GPIO4GPIO4TOUCH_CHANNEL2
20GPIO5GPIO5TOUCH_CHANNEL3
21GPIO6GPIO6TOUCH_CHANNEL4
22GPIO7GPIO7TOUCH_CHANNEL5
23GPIO8GPIO8TOUCH_CHANNEL6
24GPIO9GPIO9TOUCH_CHANNEL7
25GPIO10GPIO10TOUCH_CHANNEL8
26GPIO11GPIO11TOUCH_CHANNEL9
27GPIO12GPIO12TOUCH_CHANNEL10
28GPIO13GPIO13TOUCH_CHANNEL11
29GPIO20GPIO20ADC1_CHANNEL4
30GPIO21GPIO21ADC1_CHANNEL5
31GPIO22GPIO22ADC1_CHANNEL6
32GPIO23GPIO23ADC1_CHANNEL7
33GNDGround pin
34DSI_DATAP1MIPI-DSI data signal line
35DSI_DATAN1MIPI-DSI data signal line
36DSI_CLKNMIPI-DSI clock signal line
37DSI_CLKPMIPI-DSI clock signal line
38DSI_DATAP0MIPI-DSI data signal line
39DSI_DATAN0MIPI-DSI data signal line
40GNDGround pin
41CSI_DATAN0MIPI-CSI data signal line
42CSI_DATAP0MIPI-CSI data signal line
43CSI_CLKPMIPI-CSI clock signal line
44CSI_CLKNMIPI-CSI clock signal line
45CSI_DATAN1MIPI-CSI data signal line
46CSI_DATAP1MIPI-CSI data signal line
47GNDGround pin
48USB_DMUSB 2.0 high-speed pin
49USB_DPUSB 2.0 high-speed pin
50GPIO24GPIO24; USB 2.0 full-speed pinUSB1P1_N0
51GPIO25Ground pin; USB 2.0 full-speed pinUSB1P1_P0
52GNDGround pin
53GPIO26GPIO26
54GPIO27GPIO27
55GPIO28GPIO28
56GPIO29GPIO29
57GPIO30GPIO30
58GPIO31GPIO31
59GPIO32GPIO32
60GPIO33GPIO33
61GPIO34GPIO34
62GPIO35GPIO35; If GPIO36 is in pull-up mode, it can enter download mode when pulled down before power-onBOOT
63GPIO36GPIO36; It is recommended to pull up 10k resistor to 3.3VBOOT_EN
64GPIO37GPIO37
65GPIO38GPIO38
66ESP_LDO_VO4ESP32-P4 internal LDO output pin, default output 1.8V; The output voltage can be controlled by program, controlling the voltage domains of GPIO39~GPIO48
67GPIO39GPIO39
68GPIO40GPIO40
69GPIO41GPIO41
70GPIO42GPIO42
71GPIO43GPIO43
72GPIO44GPIO44
73GPIO45GPIO45
74GPIO46GPIO46
75GPIO47GPIO47
76GPIO48GPIO48
77GPIO49GPIO49ADC2_CHANNEL0
78GPIO50GPIO50ADC2_CHANNEL1
79GPIO51GPIO51ADC2_CHANNEL2
80GPIO52GPIO52ADC2_CHANNEL3
81GPIO53GPIO53ADC2_CHANNEL4
82GPIO54GPIO54ADC2_CHANNEL5
83GNDGround pin
84VBATESP32-P4 LP power supply pin, can be connected to a battery, it is recommended to connect to 3.3V by default
85ESP_3V3Power supply pin, it is recommended to connect 3.3V by default
86ESP_3V3Power supply pin, it is recommended to connect 3.3V by default
87ESP_ENESP32-P4 enable pin, default pulled high to enable
88GPIO0XTAL_32K_NGPIO1, can be connected with GPIO0 to 32.768KHz crystal oscillator, LP system crystal source

Processing Temperature Curve

  • The module is processed using lead-free technology. If there is a secondary SMT processing in the future, it is recommended that the module only undergo reflow soldering once


IPEX Gen 1 Antenna Holder Drawing


Resources

Schematic Diagram

3D Diagram

PCB Packaging Drawing

Datasheets

Softwares

FAQ

Support

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Email: services01@spotpear.com

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